On Wed, Apr 24, 2024 at 02:21:22PM +0800, Richard Zhu wrote: > Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding. > Introduce one HSIO configuration 'fsl,hsio-cfg', which need be set at > initialization according to board design. > > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx> > --- > .../bindings/phy/fsl,imx8qm-hsio.yaml | 146 ++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > > diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > new file mode 100644 > index 000000000000..3e2824d1616c > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > @@ -0,0 +1,146 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8QM SoC series HSIO SERDES PHY > + > +maintainers: > + - Richard Zhu <hongxing.zhu@xxxxxxx> > + > +properties: > + compatible: > + enum: > + - fsl,imx8qm-hsio > + - fsl,imx8qxp-hsio > + reg: > + minItems: 4 > + maxItems: 4 > + > + "#phy-cells": > + const: 3 > + description: > + The first defines the type of the PHY refer to the include phy.h. > + The second defines controller index. > + The third defines the lane mask of the lane ID, indicated which > + lane is used by the PHY. They are defined as HSIO_LAN* in > + dt-bindings/phy/phy-imx8-pcie.h > + > + reg-names: > + items: > + - const: reg > + - const: phy > + - const: ctrl > + - const: misc > + > + clocks: > + minItems: 5 > + maxItems: 14 > + > + clock-names: > + minItems: 5 > + maxItems: 14 > + > + fsl,hsio-cfg: > + description: Refer macro HSIO_CFG* include/dt-bindings/phy/phy-imx8-pcie.h. > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + fsl,refclk-pad-mode: > + description: > + Specifies the mode of the refclk pad used. It can be UNUSED(PHY > + refclock is derived from SoC internal source), INPUT(PHY refclock > + is provided externally via the refclk pad) or OUTPUT(PHY refclock > + is derived from SoC internal source and provided on the refclk pad). > + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants > + to be used. > + $ref: /schemas/types.yaml#/definitions/uint32 > + default: IMX8_PCIE_REFCLK_PAD_OUTPUT My comments on this are still not addressed. Please go back and read my comments about this property on v1.
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