[PATCH 2/3] arm64: dts: imx93: add enet_clk_sel

[Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>]

The ENET_CLK_SEL register is at offset 0x2c in the wakeupmix_gpr
register and needed to set the TX_CLK direction in case of RMII mode.

Signed-off-by: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/freescale/imx93.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index 601c94e1fac8e..116ff9c15709b 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -1051,6 +1051,7 @@ eqos: ethernet@428a0000 {
 							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
 				assigned-clock-rates = <100000000>, <250000000>;
 				intf_mode = <&wakeupmix_gpr 0x28>;
+				enet_clk_sel = <&wakeupmix_gpr 0x2c>;
 				snps,clk-csr = <0>;
 				status = "disabled";
 			};

-- 
2.43.2