On Mon, 15 Apr 2024 at 21:23, Alexandru Gagniuc <mr.nuke.me@xxxxxxxxx> wrote: > > Add support for the gen3x2 PCIe PHY on IPQ9574, ported form downstream > 5.4 kernel. Only the serdes and pcs_misc tables are new, the others > being reused from IPQ8074 and IPQ6018 PHYs. > > Signed-off-by: Alexandru Gagniuc <mr.nuke.me@xxxxxxxxx> > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++- > .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++ > 2 files changed, 149 insertions(+), 1 deletion(-) > [skipped] > @@ -2448,7 +2542,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) > > /* list of clocks required by phy */ > static const char * const qmp_pciephy_clk_l[] = { > - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", > + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "anoc", "snoc" Are the NoC clocks really necessary to drive the PHY? I think they are usually connected to the controllers, not the PHYs. > }; > > /* list of regulators */ > @@ -2499,6 +2593,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = { > .rx = 0x0400, > }; > > +static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = { > + .serdes = 0, > + .pcs = 0x1000, > + .pcs_misc = 0x1400, > + .tx = 0x0200, > + .rx = 0x0400, > + .tx2 = 0x0600, > + .rx2 = 0x0800, > +}; > + > static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = { > .serdes = 0, > .pcs = 0x0a00, > @@ -2728,6 +2832,33 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { > .phy_status = PHYSTATUS, > }; > > +static const struct qmp_phy_cfg ipq9574_pciephy_gen3x2_cfg = { > + .lanes = 2, > + > + .offsets = &qmp_pcie_offsets_ipq9574, > + > + .tbls = { > + .serdes = ipq9574_gen3x2_pcie_serdes_tbl, > + .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl), > + .tx = ipq8074_pcie_gen3_tx_tbl, > + .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), > + .rx = ipq6018_pcie_rx_tbl, > + .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), > + .pcs = ipq6018_pcie_pcs_tbl, > + .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), > + .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl, > + .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl), > + }, > + .reset_list = ipq8074_pciephy_reset_l, > + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), > + .vreg_list = NULL, > + .num_vregs = 0, > + .regs = pciephy_v4_regs_layout, So, is it v4 or v5? > + > + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > + .phy_status = PHYSTATUS, > +}; > + > static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { > .lanes = 2, > -- With best wishes Dmitry