Am 14.04.24 um 14:58 schrieb Josua Mayer: > Add description for the SolidRun CN9131 SolidWAN, based on CN9130 SoM > with an extra communication processor on the carrier board. > > This board differentiates itself from CN9130 Clearfog by providing > additional SoC native network interfaces and pci buses: > 2x 10Gbps SFP+ > 4x 1Gbps RJ45 > 1x miniPCI-E > 1x m.2 b-key with sata, usb-2.0 and usb-3.0 > 1x m.2 m-key with pcie and usb-2.0 > 1x m.2 b-key with pcie, usb-2.0, usb-3.0 and 2x sim slots > 1x mpcie with pcie only > 2x type-a usb-2.0/3.0 > > Signed-off-by: Josua Mayer <josua@xxxxxxxxxxxxx> > --- > arch/arm64/boot/dts/marvell/Makefile | 1 + > arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts | 653 +++++++++++++++++++++ > 2 files changed, 654 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile > index 019f2251d696..16f9d7156d9f 100644 > --- a/arch/arm64/boot/dts/marvell/Makefile > +++ b/arch/arm64/boot/dts/marvell/Makefile > @@ -30,3 +30,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb > dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb > +dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb > diff --git a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts > new file mode 100644 > index 000000000000..ba7dd55abfb4 > --- /dev/null > +++ b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts > @@ -0,0 +1,653 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2024 Josua Mayer <josua@xxxxxxxxxxxxx> > + * > + * DTS for SolidRun CN9130 Clearfog Base. > + * > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/input/input.h> > +#include <dt-bindings/leds/common.h> > + > +#include "cn9130.dtsi" > +#include "cn9130-sr-som.dtsi" > + > +/* > + * Instantiate the external CP115 > + */ > + > +#define CP11X_NAME cp1 > +#define CP11X_BASE f4000000 > +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) > +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 > +#define CP11X_PCIE0_BASE f4600000 > +#define CP11X_PCIE1_BASE f4620000 > +#define CP11X_PCIE2_BASE f4640000 > + > +#include "armada-cp115.dtsi" > + > +#undef CP11X_NAME > +#undef CP11X_BASE > +#undef CP11X_PCIEx_MEM_BASE > +#undef CP11X_PCIEx_MEM_SIZE > +#undef CP11X_PCIE0_BASE > +#undef CP11X_PCIE1_BASE > +#undef CP11X_PCIE2_BASE > + This is not very pretty, but shared between all CN9313 designs. CN9132 designs will even have two of these with different addresses. Is this worth moving into a dtsi? I see two options then: 1. introduce cn9131.dtsi (which includes cn9130.dtsi). Boards then can simply include cn9131.dtsi and skip cn9130.dtsi 2. introduce a standalone cn9130-cp1.dtsi which only instantiates cp1, and does not include cn9130.dtsi. Boards should include everything they need, e.g. cn9130.dtsi + cn9130-cp1.dtsi + cn9130-cp2.dtsi
