Am 14.04.24 um 14:58 schrieb Josua Mayer:
> Add description for the SolidRun CN9130 SoM, and Clearfog Base / Pro
> reference boards.
>
> The SoM has been designed as a pin-compatible replacement for the older
> Armada 388 based SoM. Therefore it supports the same boards and a
> similar feature set.
>
> Most notable upgrades:
> - 4x Cortex-A72
> - 10Gbps SFP
> - Both eMMC and SD supported at the same time
>
> The developer first supporting this product at SolidRun decided to use
> different filenames for the DTBs: Armada 388 uses the full
> "clearfog" string while cn9130 uses the abbreviation "cf".
> This name is already hard-coded in pre-installed vendor u-boot and can
> not be changed easily.
>
> NOTICE IN CASE ANYBODY WANTS TO SELF-UPGRADE:
> CN9130 SoM has a different footprint from Armada 388 SoM.
> Components on the carrier board below the SoM may collide causing
> damage, such as on Clearfog Base.
>
> Signed-off-by: Josua Mayer <josua@xxxxxxxxxxxxx>
> ---
Previous version had received an ack from Krzysztof Kozlowski,
which I dropped because I made additional changes.
To simplify review, please find below
the incremental changes from v2 to v3:
>From 8e32db3d5b4feced98f26695780c5253b928bb14 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@xxxxxxxxxxxxx>
Date: Fri, 5 Apr 2024 17:35:52 +0200
Subject: [PATCH] arm64: dts: cn9131-cf-solidwan: minor tweaks
1. move legacy armada-388 netdev aliases to carrier:
Legacy port numbering is only useful for platforms previously using
the armada-388 som, and can be achieved in carrier dts.
SoM dts can follow soc port numbering.
2. Fix two status property mistakes: one duplicate and one not last
property.
3. Add pinctrl for spi chip-select 1, which is exposed on carrier
mikrobus header.
4. Specify spi bus max frequencies based on som limitations.
Signed-off-by: Josua Mayer <josua@xxxxxxxxxxxxx>
---
arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts | 10 ++++++++++
arch/arm64/boot/dts/marvell/cn9130-cf.dtsi | 4 ++++
arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi | 13 +++++++------
3 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts b/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts
index 0b95d5f7acfd..15c74d584dbd 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts
@@ -336,6 +336,16 @@ rear_button_pins: cp0-rear-button-pins {
marvell,pins = "mpp32";
marvell,function = "gpio";
};
+
+ cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
+ marvell,pins = "mpp12";
+ marvell,function = "spi1";
+ };
+};
+
+&cp0_spi1 {
+ /* add pin for chip-select 1 on mikrobus */
+ pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>;
};
/*
diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi b/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
index 53aedddf0e26..dcbbdbb9b25a 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
@@ -8,6 +8,10 @@
/ {
aliases {
+ /* label nics same order as armada 388 clearfog */
+ ethernet0 = &cp0_eth2;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth0;
i2c1 = &cp0_i2c1;
mmc1 = &cp0_sdhci0;
};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi
index ec08066fb6e8..8f0238a45a58 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi
@@ -11,10 +11,9 @@ / {
compatible = "solidrun,cn9130-sr-som", "marvell,cn9130";
aliases {
- /* label nics like armada-388 som */
- ethernet0 = &cp0_eth2;
+ ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
- ethernet2 = &cp0_eth0;
+ ethernet2 = &cp0_eth2;
i2c0 = &cp0_i2c0;
mmc0 = &ap_sdhci0;
rtc0 = &cp0_rtc;
@@ -82,7 +81,6 @@ &cp0_eth2 {
};
&cp0_i2c0 {
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
clock-frequency = <100000>;
@@ -96,8 +94,8 @@ som_eeprom: eeprom@53 {
};
&cp0_mdio {
- status = "okay";
pinctrl-0 = <&cp0_mdio_pins>;
+ status = "okay";
/* assembly option */
cp0_eth2_phy: ethernet-phy@0 {
@@ -109,11 +107,14 @@ &cp0_spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi1_pins>;
+ /* max speed limited by a mux */
+ spi-max-frequency = <1800000000>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <10000000>;
+ /* read command supports max. 50MHz */
+ spi-max-frequency = <50000000>;
};
};
--
2.35.3
