On Fri, Apr 12, 2024 at 11:27:23AM +0100, Conor Dooley wrote: > On Thu, Apr 11, 2024 at 09:11:09PM -0700, Charlie Jenkins wrote: > > The xtheadvector ISA extension is described on the T-Head extension spec > > Github page [1]. > > > > [1] https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadvector.adoc > > Link: <foo> [1] > > > > > Signed-off-by: Charlie Jenkins <charlie@xxxxxxxxxxxx> > > --- > > Documentation/devicetree/bindings/riscv/extensions.yaml | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > > index 468c646247aa..3fd9dcf70662 100644 > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > > @@ -477,6 +477,10 @@ properties: > > latency, as ratified in commit 56ed795 ("Update > > riscv-crypto-spec-vector.adoc") of riscv-crypto. > > > > + # vendor extensions, each extension sorted alphanumerically under the > > + # vendor they belong to. Vendors are sorted alphanumerically as well. > > + > > + # Andes > > - const: xandespmu > > description: > > The Andes Technology performance monitor extension for counter overflow > > @@ -484,5 +488,10 @@ properties: > > Registers in the AX45MP datasheet. > > https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf > > > > + # T-HEAD > > + - const: xtheadvector > > + description: > > + The T-HEAD specific 0.7.1 vector implementation. > > This needs the link and a SHA or some other reference to the version > of the document. Okay will add, thank you. - Charlie > > Thanks, > Conor. > > > + > > additionalProperties: true > > ... > > > > -- > > 2.44.0 > >
