This patch series ended up much larger than expected, please bear with me! The goal here is to support vendor extensions, starting at probing the device tree and ending with reporting to userspace. The main design objective was to allow vendors to operate independently of each other. This has been achieved by delegating vendor extensions to a new struct "hart_isa_vendor" which is a counterpart to "hart_isa". Each vendor will have their own list of extensions they support. Each vendor will have a "namespace" to themselves which is set at the key values of 0x8000 - 0x8080. It is up to the vendor's disgression how they wish to allocate keys in the range for their vendor extensions. Reporting to userspace follows a similar story, leveraging the hwprobe syscall. There is a new hwprobe key RISCV_HWPROBE_KEY_VENDOR_EXT_0 that is used to request supported vendor extensions. The vendor extension keys are disambiguated by the vendor associated with the cpumask passed into hwprobe. The entire 64-bit key space is available to each vendor. On to the xtheadvector specific code. xtheadvector is a custom extension that is based upon riscv vector version 0.7.1 [1]. All of the vector routines have been modified to support this alternative vector version based upon whether xtheadvector was determined to be supported at boot. I have tested this with an Allwinner Nezha board. I ran into issues booting the board on 6.9-rc1 so I applied these patches to 6.8. There are a couple of minor merge conflicts that do arrise when doing that, so please let me know if you have been able to boot this board with a 6.9 kernel. I used SkiffOS [2] to manage building the image, but upgraded the U-Boot version to Samuel Holland's more up-to-date version [3] and changed out the device tree used by U-Boot with the device trees that are present in upstream linux and this series. Thank you Samuel for all of the work you did to make this task possible. To test the integration, I used the riscv vector kselftests. I modified the test cases to be able to more easily extend them, and then added a xtheadvector target that works by calling hwprobe and swapping out the vector asm if needed. [1] https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc [2] https://github.com/skiffos/SkiffOS/tree/master/configs/allwinner/nezha [3] https://github.com/smaeul/u-boot/commit/2e89b706f5c956a70c989cd31665f1429e9a0b48 Signed-off-by: Charlie Jenkins <charlie@xxxxxxxxxxxx> --- Charlie Jenkins (18): dt-bindings: riscv: Add vendorid and archid riscv: cpufeature: Fix thead vector hwcap removal dt-bindings: riscv: Add xtheadvector ISA extension description riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree riscv: Fix extension subset checking riscv: Extend cpufeature.c to detect vendor extensions riscv: Optimize riscv_cpu_isa_extension_(un)likely() riscv: Introduce vendor variants of extension helpers riscv: uaccess: Add alternative for xtheadvector uaccess riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT riscv: Create xtheadvector file riscv: vector: Support xtheadvector save/restore riscv: hwprobe: Disambiguate vector and xtheadvector in hwprobe riscv: hwcap: Add v to hwcap if xtheadvector enabled riscv: hwprobe: Add vendor extension probing riscv: hwprobe: Document vendor extensions and xtheadvector extension selftests: riscv: Fix vector tests selftests: riscv: Support xtheadvector in vector tests Heiko Stuebner (1): RISC-V: define the elements of the VCSR vector CSR Documentation/arch/riscv/hwprobe.rst | 12 + Documentation/devicetree/bindings/riscv/cpus.yaml | 11 + .../devicetree/bindings/riscv/extensions.yaml | 9 + arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 4 +- arch/riscv/include/asm/cpufeature.h | 143 +++++++--- arch/riscv/include/asm/csr.h | 13 + arch/riscv/include/asm/hwcap.h | 23 ++ arch/riscv/include/asm/hwprobe.h | 4 +- arch/riscv/include/asm/sbi.h | 2 + arch/riscv/include/asm/vector.h | 228 ++++++++++++---- arch/riscv/include/asm/xtheadvector.h | 25 ++ arch/riscv/include/uapi/asm/hwprobe.h | 10 +- arch/riscv/kernel/cpu.c | 20 ++ arch/riscv/kernel/cpufeature.c | 264 +++++++++++++++--- arch/riscv/kernel/kernel_mode_vector.c | 4 +- arch/riscv/kernel/sys_hwprobe.c | 59 ++++- arch/riscv/kernel/vector.c | 22 +- arch/riscv/lib/uaccess.S | 1 + tools/testing/selftests/riscv/vector/.gitignore | 3 +- tools/testing/selftests/riscv/vector/Makefile | 17 +- .../selftests/riscv/vector/v_exec_initval_nolibc.c | 93 +++++++ tools/testing/selftests/riscv/vector/v_helpers.c | 66 +++++ tools/testing/selftests/riscv/vector/v_helpers.h | 7 + tools/testing/selftests/riscv/vector/v_initval.c | 22 ++ .../selftests/riscv/vector/v_initval_nolibc.c | 68 ----- .../selftests/riscv/vector/vstate_exec_nolibc.c | 20 +- .../testing/selftests/riscv/vector/vstate_prctl.c | 295 ++++++++++++--------- 27 files changed, 1114 insertions(+), 331 deletions(-) --- base-commit: 4cece764965020c22cff7665b18a012006359095 change-id: 20240411-dev-charlie-support_thead_vector_6_9-1591fc2a431d -- - Charlie
