On Wed, Apr 10, 2024 at 09:48:30AM +0900, Yoshihiro Shimoda wrote:
> This driver can reuse other R-Car Gen4 SoCs support like r8a779g0 and
> r8a779h0. However, r8a779g0 and r8a779h0 require other initializing
> settings that differ than r8a779f0. So, add a new function pointer
> .ltssm_enable() for it. No behavior changes.
>
> After applied this patch, probing SoCs by rcar_gen4_pcie_of_match[]
> will be changed like below:
>
> - r8a779f0 as "renesas,r8a779f0-pcie" and "renesas,r8a779f0-pcie-ep"
>
If r8a779f0 SoC can work with the existing 'renesas,rcar-gen4-pcie' and
'renesas,rcar-gen4-pcie-ep' compatibles, then you should just leave it as it is
and add a new compatible with dedicated callbacks for only r8a779g0 and
r8a779h0.
- Mani
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pcie-rcar-gen4.c | 41 ++++++++++++++++++---
> 1 file changed, 36 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> index da2821d6efce..47ec394885f5 100644
> --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> @@ -48,7 +48,9 @@
> #define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
> #define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
>
> +struct rcar_gen4_pcie;
> struct rcar_gen4_pcie_platdata {
> + int (*ltssm_enable)(struct rcar_gen4_pcie *rcar);
> enum dw_pcie_device_mode mode;
> };
>
> @@ -61,8 +63,8 @@ struct rcar_gen4_pcie {
> #define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
>
> /* Common */
> -static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
> - bool enable)
> +static void rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar,
> + bool enable)
> {
> u32 val;
>
> @@ -127,9 +129,13 @@ static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
> static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
> {
> struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> - int i, changes;
> + int i, changes, ret;
>
> - rcar_gen4_pcie_ltssm_enable(rcar, true);
> + if (rcar->platdata->ltssm_enable) {
> + ret = rcar->platdata->ltssm_enable(rcar);
> + if (ret)
> + return ret;
> + }
>
> /*
> * Require direct speed change with retrying here if the link_gen is
> @@ -157,7 +163,7 @@ static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
> {
> struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
>
> - rcar_gen4_pcie_ltssm_enable(rcar, false);
> + rcar_gen4_pcie_ltssm_control(rcar, false);
> }
>
> static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
> @@ -504,6 +510,23 @@ static void rcar_gen4_pcie_remove(struct platform_device *pdev)
> rcar_gen4_pcie_unprepare(rcar);
> }
>
> +static int r8a779f0_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar)
> +{
> + rcar_gen4_pcie_ltssm_control(rcar, true);
> +
> + return 0;
> +}
> +
> +static struct rcar_gen4_pcie_platdata platdata_r8a779f0_pcie = {
> + .ltssm_enable = r8a779f0_pcie_ltssm_enable,
> + .mode = DW_PCIE_RC_TYPE,
> +};
> +
> +static struct rcar_gen4_pcie_platdata platdata_r8a779f0_pcie_ep = {
> + .ltssm_enable = r8a779f0_pcie_ltssm_enable,
> + .mode = DW_PCIE_EP_TYPE,
> +};
> +
> static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie = {
> .mode = DW_PCIE_RC_TYPE,
> };
> @@ -513,6 +536,14 @@ static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie_ep = {
> };
>
> static const struct of_device_id rcar_gen4_pcie_of_match[] = {
> + {
> + .compatible = "renesas,r8a779f0-pcie",
> + .data = &platdata_r8a779f0_pcie,
> + },
> + {
> + .compatible = "renesas,r8a779f0-pcie-ep",
> + .data = &platdata_r8a779f0_pcie_ep,
> + },
> {
> .compatible = "renesas,rcar-gen4-pcie",
> .data = &platdata_rcar_gen4_pcie,
> --
> 2.25.1
>
>
--
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