Hi Francesco,
On Tue Apr 2, 2024 at 6:58 PM CEST, Francesco Dolcini wrote:
> On Tue, Apr 02, 2024 at 05:18:02PM +0200, Michael Walle wrote:
> > Device tree best practice is to disable any external interface in the
> > dtsi and just enable them if needed in the device tree. Thus, disable
> > both ethernet ports by default and just enable the one used by the EVM
> > in its device tree.
> >
> > There is no functional change.
> >
> > Signed-off-by: Michael Walle <mwalle@xxxxxxxxxx>
> > ---
> > This should also be true for all the other SoCs. But I don't wanted to
> > touch all the (older) device trees. j722s is pretty new, so there we
> > should get it right.
> > ---
> > arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 5 +----
> > arch/arm64/boot/dts/ti/k3-j722s.dtsi | 8 ++++++++
> > 2 files changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> > index d045dc7dde0c..afe7f68e6a4b 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> > +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> > @@ -224,14 +224,11 @@ cpsw3g_phy0: ethernet-phy@0 {
> > };
> >
> > &cpsw_port1 {
> > + status = "okay";
>
> status should be the last property, according to the dts coding guidelines.
Thanks for pointing that out. There is
devicetree/bindings/dts-coding-style.rst, which is in fact new to
me. Up until now, I was under the impression that how this is
handled is up to the maintainer of the SoC. I know that for the NXP
Layerscape for example, the maintainer will have an eye esp. for
that. But here it seems kinda random/all over the place. That being
said, I tried to be consistent with the other cpsw* nodes.
Anyway, I'll change it to come last.
> > phy-mode = "rgmii-rxid";
> > phy-handle = <&cpsw3g_phy0>;
> > };
-michael
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