* Tony Lindgren <tony@xxxxxxxxxxx> [240327 09:39]:
> The DPLL output clocks are problematic at this point as the
> clock driver makes assumptions based on no reg property in
> _register_dpll_x2() for the ti,omap4-dpll-x2-clock. After
> the driver issues are solved, the DPLL output related clocks
> can also use the clksel binding.
Actually the driver needs changes only for clocks where there's no
reg entry. For the clocks with a reg entry like dpll_per m2 outputs,
the following seems to work based on light testing.
Regards,
Tony
8< -----------------
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -1425,6 +1425,7 @@ dpll_per_byp_mux: clock@23 {
};
};
+ /* CM_CLKSEL_DPLL_PER */
dpll_per_ck: clock@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
@@ -1433,16 +1434,43 @@ dpll_per_ck: clock@140 {
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
- dpll_per_m2_ck: clock-dpll-per-m2-8@150 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clock-output-names = "dpll_per_m2_ck";
- clocks = <&dpll_per_ck>;
- ti,max-div = <31>;
- ti,autoidle-shift = <8>;
- reg = <0x0150>;
- ti,index-starts-at-one;
- ti,invert-autoidle-bit;
+ /* CM_DIV_M2_DPLL_PER */
+ clock@150 {
+ compatible = "ti,clksel";
+ reg = <0x150>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll_per_m2x2_ck: clock@0 {
+ reg = <0>;
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2x2_ck";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_m2_ck: clock@8 {
+ compatible = "fixed-factor-clock";
+ reg = <8>;
+ #clock-cells = <0>;
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ clock-output-names = "dpll_per_m2_ck";
+ };
+
+ dpll_per_x2_ck: clock@10 {
+ reg = <10>;
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_per_x2_ck";
+ clocks = <&dpll_per_ck>;
+ };
};
func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
@@ -1503,13 +1531,6 @@ dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {
ti,invert-autoidle-bit;
};
- dpll_per_x2_ck: clock-dpll-per-x2 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-x2-clock";
- clock-output-names = "dpll_per_x2_ck";
- clocks = <&dpll_per_ck>;
- };
-
dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -1558,18 +1579,6 @@ dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {
ti,invert-autoidle-bit;
};
- dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clock-output-names = "dpll_per_m2x2_ck";
- clocks = <&dpll_per_x2_ck>;
- ti,max-div = <31>;
- ti,autoidle-shift = <8>;
- reg = <0x0150>;
- ti,index-starts-at-one;
- ti,invert-autoidle-bit;
- };
-
dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
--
2.44.0
