>
> On Fri, Mar 15, 2024 at 05:55:51PM +0800, Xu Yang wrote:
> > This driver is initinally used to support imx93 Soc and now it's time to
> > add support for imx95 Soc. However, some macro definitions and events are
> > different on these two Socs. For preparing imx95 supports, this will
> > refactor driver for imx93.
> >
> > Signed-off-by: Xu Yang <xu.yang_2@xxxxxxx>
> >
> > ---
> > Changes in v4:
> > - new patch
> > Changes in v5:
> > - use is_visible to hide unwanted attributes as suggested by Will
> > Changes in v6:
> > - improve imx93_ddr_perf_monitor_config()
> > Changes in v7:
> > - improve imx93_ddr_perf_monitor_config() as suggested by Frank
> > ---
> > drivers/perf/fsl_imx9_ddr_perf.c | 80 +++++++++++++++++++-------------
> > 1 file changed, 47 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
> > index 4fdf8bcf6646..5537f4e07852 100644
> > --- a/drivers/perf/fsl_imx9_ddr_perf.c
> > +++ b/drivers/perf/fsl_imx9_ddr_perf.c
> > @@ -11,14 +11,14 @@
> > #include <linux/perf_event.h>
> >
> > /* Performance monitor configuration */
> > -#define PMCFG1 0x00
> > -#define PMCFG1_RD_TRANS_FILT_EN BIT(31)
> > -#define PMCFG1_WR_TRANS_FILT_EN BIT(30)
> > -#define PMCFG1_RD_BT_FILT_EN BIT(29)
> > -#define PMCFG1_ID_MASK GENMASK(17, 0)
> > +#define PMCFG1 0x00
> > +#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31)
> > +#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30)
> > +#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29)
> > +#define MX93_PMCFG1_ID_MASK GENMASK(17, 0)
> >
> > -#define PMCFG2 0x04
> > -#define PMCFG2_ID GENMASK(17, 0)
> > +#define PMCFG2 0x04
> > +#define MX93_PMCFG2_ID GENMASK(17, 0)
> >
> > /* Global control register affects all counters and takes priority over local control registers */
> > #define PMGC0 0x40
> > @@ -76,6 +76,11 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = {
> > .identifier = "imx93",
> > };
> >
> > +static inline bool is_imx93(struct ddr_pmu *pmu)
> > +{
> > + return pmu->devtype_data == &imx93_devtype_data;
> > +}
> > +
> > static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
> > {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
> > { /* sentinel */ }
> > @@ -185,7 +190,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)),
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)),
> > IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)),
> > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)),
> > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/
> >
> > /* counter3 specific events */
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)),
> > @@ -197,7 +202,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)),
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)),
> > IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)),
> > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)),
> > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/
> >
> > /* counter4 specific events */
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)),
> > @@ -209,7 +214,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)),
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)),
> > IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)),
> > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)),
> > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/
> >
> > /* counter5 specific events */
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)),
> > @@ -244,9 +249,26 @@ static struct attribute *ddr_perf_events_attrs[] = {
> > NULL,
> > };
> >
> > +static umode_t
> > +ddr_perf_events_attrs_is_visible(struct kobject *kobj,
> > + struct attribute *attr, int unused)
> > +{
> > + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj));
> > + struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
> > +
> > + if ((!strcmp(attr->name, "eddrtq_pm_rd_trans_filt") ||
> > + !strcmp(attr->name, "eddrtq_pm_wr_trans_filt") ||
> > + !strcmp(attr->name, "eddrtq_pm_rd_beat_filt")) &&
> > + !is_imx93(ddr_pmu))
> > + return 0;
>
> I think use name to check visible is not good enough.
Yeah, I failed to find out a better way to deal with it.
>
> struct imx9_pmu_events_attr
> {
> struct perf_pmu_events_attr perf_attr;
> void * drv_data;
> };
>
> #define IMX9_DDR_PMU_EVENT_ATTR_COM(_name, _id, drv_data) \
> (&((struct imx9_pmu_events_attr[]) { \
> { .perf_attr.attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\
> .perf_attr.id = _id,
> .drv_data = drv_data,
> } \
> })[0].perf_attr.attr.attr)
>
> #define IMX9_DDR_PMU_EVENT_ATTR(_namee, _id,)
> IMX9_DDR_PMU_EVENT_ATTR_COM(_name, _id, NULL)
>
> #define IMX93_DDR_PMU_EVENT_ATTR(_name, _id)
> IMX9_DDR_PMU_EVENT_ATTR_COM(_name, _id, &imx93_devtype_data)
>
> So
>
> ddr_perf_events_attrs_is_visible()
> {
> struct imx9_pmu_events_attr *imx9_attr = container_of(attr, imx9_pmu_events_attr, perf_attr)
>
> if (!imx9_attr->drv_data)
> return attr->mode;
>
> if (imx9_attr->drv_data ! = ddr_pmu->drv_data)
> return 0;
>
> return attr->mode;
> }
I've tried your suggestion, it works and make sense for me.
I'll integrate this in next version.
Thanks,
Xu Yang
>
> Frank
>
> > +
> > + return attr->mode;
> > +}
> > +
> > static const struct attribute_group ddr_perf_events_attr_group = {
> > .name = "events",
> > .attrs = ddr_perf_events_attrs,
> > + .is_visible = ddr_perf_events_attrs_is_visible,
> > };
> >
> > PMU_FORMAT_ATTR(event, "config:0-15");
> > @@ -368,36 +390,28 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
> > }
> > }
> >
> > -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
> > - int counter, int axi_id, int axi_mask)
> > +static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
> > + int counter, int axi_id, int axi_mask)
> > {
> > u32 pmcfg1, pmcfg2;
> > + u32 mask[] = { MX93_PMCFG1_RD_TRANS_FILT_EN,
> > + MX93_PMCFG1_WR_TRANS_FILT_EN,
> > + MX93_PMCFG1_RD_BT_FILT_EN };
> >
> > pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
> >
> > - if (counter == 2 && event == 73)
> > - pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN;
> > - else if (counter == 2 && event != 73)
> > - pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN;
> > -
> > - if (counter == 3 && event == 73)
> > - pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN;
> > - else if (counter == 3 && event != 73)
> > - pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN;
> > -
> > - if (counter == 4 && event == 73)
> > - pmcfg1 |= PMCFG1_RD_BT_FILT_EN;
> > - else if (counter == 4 && event != 73)
> > - pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN;
> > + if (counter >= 2 && counter <= 4)
> > + pmcfg1 = event == 73 ? pmcfg1 | mask[counter - 2] :
> > + pmcfg1 & ~mask[counter - 2];
> >
> > - pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF);
> > - pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, axi_mask);
> > - writel(pmcfg1, pmu->base + PMCFG1);
> > + pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF);
> > + pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, axi_mask);
> > + writel_relaxed(pmcfg1, pmu->base + PMCFG1);
> >
> > pmcfg2 = readl_relaxed(pmu->base + PMCFG2);
> > - pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF);
> > - pmcfg2 |= FIELD_PREP(PMCFG2_ID, axi_id);
> > - writel(pmcfg2, pmu->base + PMCFG2);
> > + pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF);
> > + pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, axi_id);
> > + writel_relaxed(pmcfg2, pmu->base + PMCFG2);
> > }
> >
> > static void ddr_perf_event_update(struct perf_event *event)
> > @@ -513,7 +527,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
> > ddr_perf_event_start(event, flags);
> >
> > /* read trans, write trans, read beat */
> > - ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
> > + imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
> >
> > return 0;
> > }
> > --
> > 2.34.1
> >
