On 3/12/2024 9:08 AM, Jakub Kicinski wrote:
On Tue, 12 Mar 2024 08:49:21 +0800 Yang Xiwen wrote:
Still not very correct here. In downstream the core can also have an
external PHY. The internal phy is also optional. So maybe this clock
should be optional.
You are responding to yourself 4 min after posting?
What is the purpose of your comments?
Just to remind others or myself this can be improved. But i think it's
ready to be applied. There won't be similar design in mainline soon i think.
It's a fairly uncommon thing to do, normally such notes should either
be comments in the code or notes in the commit message.
Yeah. Maybe i can try to improve this in the next 6 weeks. But without
the hardware to test, i can hardly say my implementation is correct or not.
In any case - the merge window for v6.9 has started, we won't be able
to merge these changes for the next 2 weeks :(
It's sad to wait for another 6 weeks till v6.10. But i'm okay with it,
since i still have a lot of other patches pending to be applied for
Hi3798MV200 SoC.
--
Regards,
Yang Xiwen
