On 2024-03-04 10:22, Anand Moon wrote:
On Mon, 4 Mar 2024 at 00:35, Dragan Simic <dsimic@xxxxxxxxxxx> wrote:
Add missing cache information to the Rockchip RK3328 SoC dtsi, to
allow
the userspace, which includes /proc/cpuinfo and lscpu(1), to present
proper
RK3328 cache information.
While there, use a more self-descriptive label for the L2 cache node,
which
also makes it more consistent with other SoC dtsi files.
The cache parameters for the RK3328 dtsi were obtained and partially
derived
by hand from the cache size and layout specifications found in the
following
datasheets, official vendor websites, and technical reference manuals:
- Rockchip RK3328 datasheet, version 1.4
- https://opensource.rock-chips.com/wiki_RK3328, accessed on
2024-02-28
- ARM Cortex-A53 revision r0p3 TRM, version E
For future reference, here's a brief summary of the documentation:
- All caches employ the 64-byte cache line length
- Each Cortex-A53 core has 32 KB of L1 2-way, set-associative
instruction
cache and 32 KB of L1 4-way, set-associative data cache
- The entire SoC has 256 KB of unified L2 16-way, set-associative
cache
The RK3328 SoC dtsi is also used for the single RK3318-based supported
board.
Unfortunately, no datasheet is available for the RK3318, but some
unofficial
sources state that its L2 cache size is the same as RK3328's, so it's
perhaps
safe to assume the same for the L1 instruction and data cache sizes.
Signed-off-by: Dragan Simic <dsimic@xxxxxxxxxxx>
---
Thanks. Please add my,
Reviewed-by: Anand Moon <linux.amoon@xxxxxxxxx>
Thank you once again.
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 37
++++++++++++++++++++----
1 file changed, 32 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 7b4c15c4a9c3..ac2846c33dc9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -46,47 +46,71 @@ cpu0: cpu@0 {
cpu-idle-states = <&CPU_SLEEP>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
- next-level-cache = <&l2>;
operating-points-v2 = <&cpu0_opp_table>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
cpu-idle-states = <&CPU_SLEEP>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
- next-level-cache = <&l2>;
operating-points-v2 = <&cpu0_opp_table>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
cpu-idle-states = <&CPU_SLEEP>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
- next-level-cache = <&l2>;
operating-points-v2 = <&cpu0_opp_table>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
cpu-idle-states = <&CPU_SLEEP>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
- next-level-cache = <&l2>;
operating-points-v2 = <&cpu0_opp_table>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
idle-states {
@@ -102,10 +126,13 @@ CPU_SLEEP: cpu-sleep {
};
};
- l2: l2-cache0 {
+ l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
};
};
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