On 03/03/2024 14:26, Yangyu Chen wrote: > Add initial dts for CanMV-K230 and K230-EVB powered by Canaan Kendryte > K230 SoC [1]. > > Some key considerations: > - Only enable BigCore which is 1.6GHz RV64GCBV > > Since is there cache coherence between two cores remains a mystery since > they have a dedicated L2 Cache. And the factory SDK uses it for other OS > by default. > > Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is > CPU1, the csr.mhartid of this core is 0. > > - Support for "zba" "zbb" "zbc" "zbs" are tested by hand > > The user manual of C908 from T-Head does not document it specifically. > It just said it supports B extension V1.0-rc1. [2] > > - Support for "zicbom" is tested by hand > > Have tested with some out-of-tree drivers that need DMA and they do not > come to the dts currently. > > - Cache parameters are inferred from T-Head docs [2] and Cannan docs [1] > > L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline > L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline > L2: 256KB, PIPI 16-way set-associative, 64B Cacheline > > The numbers of cache sets are calculated from these parameters. > > - MMU only supports Sv39 > > Since T-Head docs [2] says C908 should support sv48. However, it will fail > during the kernel probe. I also tested it by hand on M-Mode software, > writing sv48 to satp.mode will not trap but will leave the csr unchanged. > > [1] https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction > [2] https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf > > Signed-off-by: Yangyu Chen <cyy@xxxxxxxxxxxx> > --- > arch/riscv/boot/dts/canaan/Makefile | 2 + > arch/riscv/boot/dts/canaan/canmv-k230.dts | 23 ++++ > arch/riscv/boot/dts/canaan/k230-evb.dts | 23 ++++ > arch/riscv/boot/dts/canaan/k230.dtsi | 146 ++++++++++++++++++++++ > 4 files changed, 194 insertions(+) > create mode 100644 arch/riscv/boot/dts/canaan/canmv-k230.dts > create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts > create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi > > diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile > index 987d1f0c41f0..b4a0ec668f9a 100644 > --- a/arch/riscv/boot/dts/canaan/Makefile > +++ b/arch/riscv/boot/dts/canaan/Makefile > @@ -5,3 +5,5 @@ dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb > dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb > dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb > dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maixduino.dtb > +dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb > +dtb-$(CONFIG_ARCH_CANAAN) += canmv-k230.dtb > \ No newline at end of file Please fix patch errors. > diff --git a/arch/riscv/boot/dts/canaan/canmv-k230.dts b/arch/riscv/boot/dts/canaan/canmv-k230.dts > new file mode 100644 > index 000000000000..09777616d30e ... > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi > new file mode 100644 > index 000000000000..4317bda38142 > --- /dev/null > +++ b/arch/riscv/boot/dts/canaan/k230.dtsi > @@ -0,0 +1,146 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2024 Yangyu Chen <cyy@xxxxxxxxxxxx> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/dts-v1/; > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "canaan,kendryte-k230"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <27000000>; > + > + cpu@0 { > + compatible = "thead,c908", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + riscv,isa = "rv64imafdcv_zba_zbb_zbc_zbs_zicbom_svpbmt"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zba", "zbb", > + "zbc", "zbs", "zicbom", "zicntr", "zicsr", > + "zifencei", "zihpm", "svpbmt"; > + riscv,cbom-block-size = <64>; > + d-cache-block-size = <64>; > + d-cache-sets = <128>; > + d-cache-size = <32768>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + next-level-cache = <&l2_cache>; > + mmu-type = "riscv,sv39"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + l2_cache: l2-cache { > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-size = <262144>; > + cache-sets = <256>; > + cache-unified; > + }; > + }; > + > + soc { > + compatible = "simple-bus"; > + interrupt-parent = <&plic>; > + #address-cells = <2>; > + #size-cells = <2>; > + dma-noncoherent; > + ranges; > + > + plic: interrupt-controller@f00000000 { > + compatible = "thead,c900-plic"; > + reg = <0xf 0x00000000 0x0 0x04000000>; > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > + interrupt-controller; > + reg-names = "control"; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <208>; > + }; > + > + clint: timer@f04000000 { > + compatible = "thead,c900-clint"; > + reg = <0xf 0x04000000 0x0 0x04000000>; > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; > + }; > + > + apb_clk: apb-clk-clock { Only MMIO-nodes go to soc. Such stubs go outside. It does not look like you tested the DTS against bindings. Please run `make dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). > + compatible = "fixed-clock"; > + clock-frequency = <50000000>; > + clock-output-names = "apb_clk"; > + #clock-cells = <0>; > + }; > + Best regards, Krzysztof
