Il 23/02/24 10:11, Chen-Yu Tsai ha scritto:
From: Ikjoon Jang <ikjn@xxxxxxxxxxxx>
mfgcfg clock is under MFG_ASYNC power domain.
Fixes: e526c9bc11f8 ("arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile")
Fixes: 37fb78b9aeb7 ("arm64: dts: mediatek: Add mt8183 power domains controller")
Signed-off-by: Weiyi Lu <weiyi.lu@xxxxxxxxxxxx>
Signed-off-by: Ikjoon Jang <ikjn@xxxxxxxxxxxx>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@xxxxxxxxxxxxx>
Signed-off-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
---
This patch is long overdue. Could we merge it for fixes for this or the
next release?
A clock controller that needs a power domain? Can you please describe the issue
that you're trying to solve with this?
It's not very uncommon but I'm not entirely convinced that this is right, because
the MFG_BG3D is a gate - and it's *not* outputting a clock rate on its own: the
mfgcfg is entirely GPU related and if there is no GPU support this clock is not
even ever needed.
MediaTek, can you please clarify if (and why) this gate clock needs a MTCMOS to
be ungated?
Thanks,
Angelo
Changes since v2:
- Rebased onto current tree
- Added Fixes tags
- Fix up subject prefix
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 93dfbf130231..774ae5d9143f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1637,6 +1637,7 @@ mfgcfg: syscon@13000000 {
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>;
};
gpu: gpu@13040000 {
