> It is not specific to AMD versions. All Cadence GEM IP versions have the > capability, but specific vendors might enable or disable it as per their > requirements. Do you mean it is an option to synthesizer it or not? So although the basic IP licensed from Cadence has it, a silicon vendor could remove it? > WOL was previously enabled via the device-tree attribute. Some users might > not leverage it. This is not typical. If the hardware supports it, we let the end user decided if they want to use it or not. So if all silicon should have it, enable it everywhere. If there is an option to save some gates and leave it out of the silicon, then we do need some per device knowledge, or a register which tells us what the synthesis options where. Andrew
