Hi, Thomas
> -----邮件原件-----
> 发件人: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
> 发送时间: 2024年2月20日 17:28
> 收件人: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>; Rob
> Herring <robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@xxxxxxxxxx>; Conor Dooley <conor+dt@xxxxxxxxxx>;
> Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
> 抄送: Leyfoon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx>; Jack Zhu
> <jack.zhu@xxxxxxxxxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx
> 主题: Re: 回复: [PATCH v2 2/2] irqchip: Add StarFive external interrupt
> controller
>
> On Sun, Feb 18 2024 at 02:36, Changhuang Liang wrote:
> >> On Mon, Jan 29 2024 at 21:58, Changhuang Liang wrote:
> > [...]
> >> > +static void starfive_intc_mod(struct starfive_irq_chip *irqc, u32
> >> > +reg, u32 mask, u32 data) {
> >> > + u32 value;
> >> > +
> >> > + value = ioread32(irqc->base + reg) & ~mask;
> >> > + data &= mask;
> >>
> >> Why?
> >>
> >
> > If I want to update the reg GENMASK(7, 4) to value 5, the data I
> > will pass in 5 << 4
>
> All call sites pass a single bit to set/clear, right? So this GENMASK argument
> does not make sense at all.
>
Yes, I will update this function
