Re: 回复: [PATCH v2 2/2] irqchip: Add StarFive external interrupt controller

[Thomas Gleixner <tglx@xxxxxxxxxxxxx>]

On Sun, Feb 18 2024 at 02:36, Changhuang Liang wrote:
>> On Mon, Jan 29 2024 at 21:58, Changhuang Liang wrote:
> [...]
>> > +static void starfive_intc_mod(struct starfive_irq_chip *irqc, u32
>> > +reg, u32 mask, u32 data) {
>> > +	u32 value;
>> > +
>> > +	value = ioread32(irqc->base + reg) & ~mask;
>> > +	data &= mask;
>> 
>> Why?
>> 
>
> If I want to update the reg  GENMASK(7, 4)  to value 5, the data I
> will pass in 5 << 4

All call sites pass a single bit to set/clear, right? So this GENMASK
argument does not make sense at all.

Thanks,

        tglx