On 16/02/2024 01:08, Samuel Holland wrote: > From: Eric Lin <eric.lin@xxxxxxxxxx> > > Add YAML DT binding documentation for the SiFive Private L2 Cache > controller. Some functionality and the corresponding register bits were > removed in the sifive,pl2cache1 version of the hardware, which creates > the unusual situation where the newer hardware's compatible string is > the fallback for the older one. > > Signed-off-by: Eric Lin <eric.lin@xxxxxxxxxx> > Co-developed-by: Samuel Holland <samuel.holland@xxxxxxxxxx> > Signed-off-by: Samuel Holland <samuel.holland@xxxxxxxxxx> > --- > > Changes in v1: > - Add back select: clause to binding > - Make sifive,pl2cache1 the fallback for sifive,pl2cache0 > - Fix the order of the reg property declaration > - Document the sifive,perfmon-counters property This is no v1. Please implement entire feedback from previous v2, v3 or whatever it was and reference old posting or continue the numbering. Best regards, Krzysztof
