This patch series adds bindings and drivers for the Performance Monitoring Units (PMUs) found in three SiFive cache controllers. Composable Cache and Extensible Cache support system-wide profiling with a single hardware instance. Private L2 Cache supports per-task profiling with a separate hardware instance per core. All three PMUs have a similar register interface and event encoding, though the set of supported events is different. The Extensible Cache additionally contains a pmCounterInhibit register which allows atomically monitoring multiple counters. All three of these cache controllers (with PMUs) have been integrated in SoCs by our customers. However, as none of those SoCs have been publicly announced yet, I cannot include SoC-specific compatible strings in this version of the devicetree bindings. This series is a follow-up to Eric Lin's series "[PATCH v2 0/3] Add SiFive Private L2 cache and PMU driver": https://lore.kernel.org/linux-riscv/20230720135125.21240-1-eric.lin@xxxxxxxxxx/ Changes in v1: - Add back select: clause to binding - Make sifive,pl2cache1 the fallback for sifive,pl2cache0 - Fix the order of the reg property declaration - Document the sifive,perfmon-counters property - Drop the non-PMU part of the PL2 cache driver, as the config register save/restore logic will be moved to M-mode - Add missing events to PL2 sets 2, 4, and 5 - Use event_base and config_base to precompute register addresses - Check event validity earlier, in the .event_init hook - Implement .filter for systems where only some CPUs have a PL2 - Only allocate percpu data when probing each PL2 instance - Reference count the `struct pmu` to fix unbind/bind crashes - Probe via DT since the PMU driver is now the only PL2 driver - Allow the driver to be built as a module Eric Lin (4): drivers/perf: Add SiFive Composable Cache PMU driver dt-bindings: cache: Add SiFive Extensible Cache controller drivers/perf: Add SiFive Extensible Cache PMU driver dt-bindings: cache: Add SiFive Private L2 Cache controller Greentime Hu (1): drivers/perf: Add SiFive Private L2 Cache PMU driver Samuel Holland (1): dt-bindings: cache: Document the sifive,perfmon-counters property .../bindings/cache/sifive,ccache0.yaml | 5 + .../cache/sifive,extensiblecache0.yaml | 136 ++++ .../bindings/cache/sifive,pl2cache0.yaml | 81 ++ drivers/perf/Kconfig | 29 + drivers/perf/Makefile | 3 + drivers/perf/sifive_ccache_pmu.c | 577 ++++++++++++++ drivers/perf/sifive_ecache_pmu.c | 675 ++++++++++++++++ drivers/perf/sifive_pl2_pmu.c | 748 ++++++++++++++++++ include/linux/cpuhotplug.h | 2 + 9 files changed, 2256 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/sifive,extensiblecache0.yaml create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache0.yaml create mode 100644 drivers/perf/sifive_ccache_pmu.c create mode 100644 drivers/perf/sifive_ecache_pmu.c create mode 100644 drivers/perf/sifive_pl2_pmu.c -- 2.43.0
