The series implements CPU clock support for Exynos850, adds CPU CMUs to
the clock driver and enables those in dts. This is the first step
towards cpufreq implementation.
The breakup by patch:
* Patch 01: Add bindings
* Patches 02..12: Prepare clk-cpu.c for Exynos850 support
* Patch 13: Add Exynos850 support
* Patch 14: Init PLLs to be in manual mode
* Patch 15: Add CPU CMUs in Exynos850 clock driver
* Patch 16: Add CPU CMUs and clocks in Exynos850 dtsi
If possible, all patches should go through Krzysztof's tree. As
inter-series dependencies go:
* All driver changes (patch 02..15) must be taken together following
the order established in this series
* Patch 16 (dts changes) depends on patch 01 (bindings additions)
* Patch 15 (driver changes) depends on patch 01 (bindings additions)
The series was tested on E850-96 board, via DebugFS with
CLOCK_ALLOW_WRITE_DEBUGFS enabled, by setting different CPU clock rates,
like this:
# cd /sys/kernel/debug/clk/cluster0_clk/
# cat clk_rate
1053000000
# echo 10000000 > clk_rate
# cat clk_rate
130000000
Of course, DVFS/cpufreq is not implemented yet, so the CPU can't be
overclocked too much right now, and the cpufreq interface is not
available too. As per the TRM, the CPU operates at a voltage level of
0.65 V, 0.75 V, 0.85 V and 1.05 V. When the voltage is 0.85 V, A55
quad-core operates at 1.6 GHz and CoreSight at 200 MHz.
To check the actual frequency, the "perf" tool was used:
# perf stat sleep 1
And to check that on a particular CPU core:
# taskset -c 4 perf stat sleep 1
Some takeaways:
* Max functional frequency right now is 1.586 GHz
* 1.742 GHz or more leads to the system freeze, as it requires
more voltage to be operational
* Max possible frequency: 2.210 GHz
* The lowest possible frequency: 130 MHz
* Default boot up frequency: 1.053 GHz
Sam Protsenko (16):
dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1
clk: samsung: Improve clk-cpu.c style
clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c
clk: samsung: Reduce params count in exynos_register_cpu_clock()
clk: samsung: Use single CPU clock notifier callback for all chips
clk: samsung: Group CPU clock functions by chip
clk: samsung: Pass actual clock controller base address to CPU_CLK()
clk: samsung: Use clk.h as a single header for Samsung CCF
clk: samsung: Pass register layout type explicitly to CLK_CPU()
clk: samsung: Keep CPU clock chip specific data in a dedicated struct
clk: samsung: Keep register offsets in chip specific structure
clk: samsung: Pass mask to wait_until_mux_stable()
clk: samsung: Add CPU clock support for Exynos850
clk: samsung: Implement manual PLL control for ARM64 SoCs
clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1
arm64: dts: exynos: Add CPU clocks
.../clock/samsung,exynos850-clock.yaml | 42 ++
arch/arm64/boot/dts/exynos/exynos850.dtsi | 26 +
drivers/clk/samsung/clk-cpu.c | 565 +++++++++++++-----
drivers/clk/samsung/clk-cpu.h | 53 +-
drivers/clk/samsung/clk-exynos-arm64.c | 44 +-
drivers/clk/samsung/clk-exynos3250.c | 4 +-
drivers/clk/samsung/clk-exynos4.c | 10 +-
drivers/clk/samsung/clk-exynos5250.c | 6 +-
drivers/clk/samsung/clk-exynos5260.c | 1 -
drivers/clk/samsung/clk-exynos5420.c | 17 +-
drivers/clk/samsung/clk-exynos5433.c | 12 +-
drivers/clk/samsung/clk-exynos850.c | 440 +++++++++++++-
drivers/clk/samsung/clk-pll.c | 2 +-
drivers/clk/samsung/clk-s3c64xx.c | 1 -
drivers/clk/samsung/clk-s5pv210.c | 1 -
drivers/clk/samsung/clk.h | 9 +-
include/dt-bindings/clock/exynos850.h | 54 ++
17 files changed, 1042 insertions(+), 245 deletions(-)
--
2.39.2
