On Thu, Feb 08, 2024 at 11:58:36AM +0530, Taniya Das wrote: > Certain clocks are not accessible on QCM6490-IDP and QCS6490-RB3GEN2 boards > thus require them to be marked protected. > > Also disable the LPASS nodes which are not to be used. > Please find a smaller patch, to make the board boot again here: https://lore.kernel.org/linux-arm-msm/20240209-qcm6490-gcc-protected-clocks-v1-1-bd3487b2e7b1@xxxxxxxxxxx/T/#u > Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx> > --- > arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 54 +++++++++++++++++++- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 50 +++++++++++++++++- > 2 files changed, 102 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > index 03e97e27d16d..425e4b87490b 100644 > --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: BSD-3-Clause > /* > - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > /dts-v1/; > @@ -415,6 +415,58 @@ > }; > }; > > +&gcc { > + protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK> ,<GCC_PCIE_1_AUX_CLK>, > + <GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>, > + <GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, > + <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, > + <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>, protected-clocks should mark the clocks that Linux must not access. With that in mind, how is listing GCC_PCIE_1_* here compatible with Krishna's patch [1], which clearly shows that Linux is expected to use pcie1. [1] https://lore.kernel.org/linux-arm-msm/20240207-enable_pcie-v1-1-b684afa6371c@xxxxxxxxxxx/ Regards, Bjorn > + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, > + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, > + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, > + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, > + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, > + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, > + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, > + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, > + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, > + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, > + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, > + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; > +}; > + > +&lpasscc { > + status = "disabled"; > +}; > + > +&lpass_audiocc { > + qcom,adsp-skip-pll; > + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, > + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, > + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, > + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, > + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, > + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; > + /delete-property/ power-domains; > +}; > + > +&lpass_aon { > + status = "disabled"; > +}; > + > +&lpass_core { > + status = "disabled"; > +}; > + > +&lpass_hm { > + status = "disabled"; > +}; > + > &qupv3_id_0 { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > index 8bb7d13d85f6..1398b84634c3 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: BSD-3-Clause > /* > - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > /dts-v1/; > @@ -413,6 +413,54 @@ > }; > }; > > +&gcc { > + protected-clocks = <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, > + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, > + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, > + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, > + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, > + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, > + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, > + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, > + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, > + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, > + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, > + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; > +}; > + > +&lpasscc { > + status = "disabled"; > +}; > + > +&lpass_audiocc { > + qcom,adsp-skip-pll; > + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, > + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, > + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, > + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, > + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, > + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; > + /delete-property/ power-domains; > +}; > + > +&lpass_aon { > + status = "disabled"; > +}; > + > +&lpass_core { > + status = "disabled"; > +}; > + > +&lpass_hm { > + status = "disabled"; > +}; > + > + > &qupv3_id_0 { > status = "okay"; > }; > -- > 2.17.1 >
