Since my previous message has been rejected due to HTML content, I'm resending it. Sorry, for the inconvenience. On 08.02.24 14:56, Andrew Lunn wrote: > [Some people who received this message don't often get email from andrew@xxxxxxx. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > This email is not from Hexagon’s Office 365 instance. Please be careful while clicking links, opening attachments, or replying to this email. > > >>> I could be reading this wrong, but it looks like >>> DP83826_CFG_DAC_MINUS_DEFAULT actually means leave the value >>> unchanged? Is there anything guaranteeing it does in fact have the >>> default value in the hardware? >>> >>> Andrew >> Yes, the datasheet clearly states the default/reset values of both >> registers VOD_CFG1 & VOD_CFG2 which are : >> - cfg_dac_minus : 30h >> - cfg_dac_plus : 10h > And the device is actually and always reset by Linux when the driver > loads? Anything the bootloader has done, or a previous kernel, will be > cleared? Now, I understand your question 🙂 To answer, DP83826_CFG_DAC_MINUS_DEFAULT will indeed leave the register unchanged. However, dp83822 driver exports a PHY callback soft_reset which does a SW reset which actually has the same effect as the HW reset pin according to the datasheet. Since the PAL enforces the call to soft_reset before config_init, in dp83826_config_init we can rely on the registers reset value. > Please add this explanation to the commit message. > > I'm being pedantic because we have had problems like this in the past. > If a register was not actually set back to the default value, the > bootloader set it to some other value, the board can work fine. Then a > board can came along which the bootloader set the wrong value, and the > default is actually needed. Fixing the driver to actually enforce the > default breaks boards... > > Andrew
