On 1/26/24 10:51 AM, Francesco Dolcini wrote:
From: Francesco Dolcini <francesco.dolcini@xxxxxxxxxxx>
Add TPM device to Mallow device tree file, the device is connected to
the SoC with SPI1/CS1, the same SPI interface is also available on an
extension header together with an additional CS0 signal.
Signed-off-by: Francesco Dolcini <francesco.dolcini@xxxxxxxxxxx>
---
arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi
index 17b93534f658..77b1beb638ad 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi
@@ -127,6 +127,16 @@ &main_spi1 {
<&pinctrl_qspi1_cs2_gpio>;
cs-gpios = <0>, <&main_gpio0 12 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
Just a heads-up, the SLB9670 datasheet says this device uses
an active low interrupt (IRQ_TYPE_LEVEL_LOW). Using TYPE_EDGE
here can cause missed interrupts if the line stays low for
multiple interrupts.
Andrew
+ spi-max-frequency = <18500000>;
+ };
};
/* Verdin UART_3 */
