Re: [PATCHv1 3/5] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS

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Hi!

You missed the AXG family with the Cortex-A53 CPU. The datasheet does not provide information on cache sizes. Given that the A113X/A113D are equipped with the Arm Cortex-A53 processor, it is assumed they use the same cache size as the S905/S905X/S905X2 models.

05/02/2024 20.19, Anand Moon wrote:
As per the S905X2 datasheet add missing cache information to the Amlogic
G12A SoC.

- Each Cortex-A53 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.

To improve system performance.

Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx>
---
No public dataheet available, since S905X2 support Arm Cortex-A53 cpu
nence used the same cache size as S905 and S905X.
---
  arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++
  1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 543e70669df5..6e1e3a3f5f18 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -17,6 +17,12 @@ cpu0: cpu@0 {
  			compatible = "arm,cortex-a53";
  			reg = <0x0 0x0>;
  			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
  			next-level-cache = <&l2>;
  			#cooling-cells = <2>;
  		};
@@ -26,6 +32,12 @@ cpu1: cpu@1 {
  			compatible = "arm,cortex-a53";
  			reg = <0x0 0x1>;
  			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
  			next-level-cache = <&l2>;
  			#cooling-cells = <2>;
  		};
@@ -35,6 +47,12 @@ cpu2: cpu@2 {
  			compatible = "arm,cortex-a53";
  			reg = <0x0 0x2>;
  			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
  			next-level-cache = <&l2>;
  			#cooling-cells = <2>;
  		};
@@ -44,6 +62,12 @@ cpu3: cpu@3 {
  			compatible = "arm,cortex-a53";
  			reg = <0x0 0x3>;
  			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
  			next-level-cache = <&l2>;
  			#cooling-cells = <2>;
  		};
@@ -52,6 +76,9 @@ l2: l2-cache0 {
  			compatible = "cache";
  			cache-level = <2>;
  			cache-unified;
+			cache-size = <0x7d000>; /* L2. 512 KB */
+			cache-line-size = <64>;
+			cache-sets = <512>;
  		};
  	};


Best regards,
--
Viacheslav Bocharov <adeep@xxxxxxxxx>




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