On Wed, Jan 31, 2024 at 11:03:25AM +0000, Kris Chaplin wrote: > Hello Krzysztof, > > On 30/01/2024 16:09, Krzysztof Kozlowski wrote: > > > > + > > > +description: | > > > + Xilinx 7 Series FPGAs support a method of loading the bitstream over a > > > + parallel port named the slave SelectMAP interface in the documentation. Only > > > + the x8 mode is supported where data is loaded at one byte per rising edge of > > > + the clock, with the MSB of each byte presented to the D0 pin. > > > + > > > + Datasheets: > > > + https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf > > > > I am surprised that AMD/Xilinx still did not update the document to > > modern naming (slave->secondary). > > Thank you for bringing this up. > > We are moving away from using non-inclusive technical terminology and are > removing non-inclusive language from our products and related collateral. > You will for some time find examples of non-inclusive language, especially > in our older products as we work to make these changes and align with > industry standards. For new IP we're ensuring that we switch and stick to > inclusive terminology, as you may have seen with my recent w1 driver > submission. > > SelectMAP is a decades-old interface and as such it is unlikely that we will > update this in all documentation dating back this time. I shall however > look to understand what is planned here for active documentation and new > driver submissions. Yes, I need review from AMD/Xilinx side. Especially the HW parts, and some namings of variables, e.g. if xilinx-core is proper for what products it supports, and won't be an issue in future. Thanks, Yilun > > regards > Kris >
