On 29/01/2024 23:56, Charles Perry wrote: > Document the slave SelectMAP interface of Xilinx 7 series FPGA. > > Signed-off-by: Charles Perry <charles.perry@xxxxxxxxxxxxxxxxxxxx> > --- > .../fpga/xlnx,fpga-slave-selectmap.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,fpga-slave-selectmap.yaml > > diff --git a/Documentation/devicetree/bindings/fpga/xlnx,fpga-slave-selectmap.yaml b/Documentation/devicetree/bindings/fpga/xlnx,fpga-slave-selectmap.yaml > new file mode 100644 > index 0000000000000..20cea24e3e39a > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/xlnx,fpga-slave-selectmap.yaml > @@ -0,0 +1,85 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-selectmap.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx Slave SelectMAP FPGA https://elixir.bootlin.com/linux/v6.8-rc2/source/Documentation/process/coding-style.rst#L338 Everywhere: compatible, title, filename, descriptions. > + > +description: | > + Xilinx 7 Series FPGAs support a method of loading the bitstream over a > + parallel port named the slave SelectMAP interface in the documentation. Only > + the x8 mode is supported where data is loaded at one byte per rising edge of > + the clock, with the MSB of each byte presented to the D0 pin. > + > + Datasheets: > + https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf I am surprised that AMD/Xilinx still did not update the document to modern naming (slave->secondary). +Cc Michal, Maybe that's something you could push it. Best regards, Krzysztof
