Hi Geert, On Wed, Jan 31, 2024 at 1:49 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Tue, Jan 30, 2024 at 11:38 AM Geert Uytterhoeven > <geert@xxxxxxxxxxxxxx> wrote: > > On Mon, Jan 29, 2024 at 2:56 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > > > On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update > > > the gpio-ranges property in RZ/Five SoC DTSI. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > > i.e. will queue in renesas-pinctrl for v6.10, as this has a hard > > dependency on the pin control patches. > > It's worse: the pin control patches without the DT patch breaks, soo. > So I have no choice but merging patch 3/4 and 4/4. > Fine by me. Cheers, Prabhakar
