On Mon, Jan 29, 2024 at 2:56 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Currently we assume all the port pins are sequential ie always PX_0 to > PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to > P28_5 which have holes in them, for example only one pin on port19 is > available and that is P19_1 and not P19_0. So to handle such cases > include pinmap for each port which would indicate the pin availability > on each port. As the pincount can be calculated based on pinmap drop this > from RZG2L_GPIO_PORT_PACK() macro. > > Previously we had a max of 7 pins on each port but on RZ/Five Port-20 > has 8 pins, so move the single pin configuration to BIT(63). > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> i.e. will queue in renesas-pinctrl for v6.9. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds