Hello, TI's J784S4 SoC has two Gen3 x4 Lane PCIe Controllers. This series adds the necessary device-tree support to enable both PCIe instances in Root Complex mode of operation by default. The device-tree overlay to enable both instances in Endpoint mode of operation is also present in this series. **NOTE** This series depends on: 1. https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240124122936.816142-1-s-vadapalli@xxxxxx/ for adding the Device ID in the bindings for J784S4 SoC. 2. https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240129104958.1139787-1-s-vadapalli@xxxxxx/ for enabling support for configuring the PCIe mode of operation, number of lanes and link speed when the System Controller node in the device-tree is modelled as a "simple-bus" which happens to be the case for J784S4 SoC: https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi#L45 3. https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240125100501.4137977-2-c-vankar@xxxxxx/ for fixing the "serdes_ln_ctrl" node in order to ensure that the PCIe lanes are mapped correctly to the corresponding Serdes Lanes. This series has been tested on top of linux-next tagged next-20240129 after applying the above dependent patches and enabling the relevant PCIe driver configs. Test Logs: 1. PCIe0 and PCIe1 in Root Complex Modes of operation with an NVMe SSD connected to PCIe0 instance and Read performance measured using hdparm: https://gist.github.com/Siddharth-Vadapalli-at-TI/6592af75ee8ba3f3bdd372a882de8b43 2. PCIe0 in Endpoint Mode on one J784S4-EVM with PCIe0 in RC Mode on other J784S4-EVM connected to each other. Enumeration of PCIe0 as an Endpoint is verified on the J784S4-EVM where PCIe0 is in RC Mode: https://gist.github.com/Siddharth-Vadapalli-at-TI/cef85519669c12894352ce081ea2a8ab 3. PCIe1 in Endpoint Mode on one J784S4-EVM with PCIe1 in RC Mode on other J784S4-EVM connected to each other. Enumeration of PCIe1 as an Endpoint is verified on the J784S4-EVM where PCIe1 is in RC Mode: https://gist.github.com/Siddharth-Vadapalli-at-TI/646d51757cffd651b51bac33d138a8ac Regards, Siddharth. Siddharth Vadapalli (3): arm64: dts: ti: k3-j784s4-main: Add PCIe nodes arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIE0 and PCIE1 EP Mode arch/arm64/boot/dts/ti/Makefile | 7 +- .../dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso | 79 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 46 ++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 84 +++++++++++++++++++ 4 files changed, 215 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso -- 2.34.1
