On 2024/1/13 3:35, Samuel Holland wrote:
Hi Conor, Chen,
On 2024-01-11 10:58 AM, Conor Dooley wrote:
On Thu, Jan 11, 2024 at 04:00:04PM +0800, Chen Wang wrote:
With this change, we describe the plls defined in system control as pllclk,
as a child node of system controller. clkgen will use pllclk as "input"
because pll clocks are parent of div clocks .
But there is another remaining question about the gate clock. For those gate
clocks controlled by CLOCK, no problem we will provide then in clkgen, but
for those gate clocks controlled by registers in SYS_CTRL, they are child
gate of the "clk_gate_rp_cpu_normal", which is a gate clock provided by
clkgen. If I extracted those SYS_CTRL gate clocks and define them in system
controller dts node, I may have to use "clk_gate_rp_cpu_normal" as their
input, it looks a bit wierd becasue there are cases where each other serves
as input. I try to draft below DTS to explan what I meant. I'm not sure if
it can work and I'd love to hear your guidance.
I'm not sure how this sort of circular relationship works for probing
works either. Stephen etc would know more than me here.
It generally works fine. The common clock framework can handle the child clock
being registered before its parent, even when using a DT (fw_name) reference.
See for example clk_core_fill_parent_index() and
clk_core_reparent_orphans_nolock() in drivers/clk/clk.c
Learned and thank you.
Regards,
Samuel
