On 2024/1/8 15:04, Krzysztof Kozlowski wrote:
On 08/01/2024 07:49, Chen Wang wrote:
From: Chen Wang <unicorn_wang@xxxxxxxxxxx>
Add bindings for the clock generator on the SG2042 RISC-V SoC.
Signed-off-by: Chen Wang <unicorn_wang@xxxxxxxxxxx>
Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
---
.../bindings/clock/sophgo,sg2042-clkgen.yaml | 53 ++++++
.../dt-bindings/clock/sophgo,sg2042-clkgen.h | 169 ++++++++++++++++++
2 files changed, 222 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h
diff --git a/Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml b/Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
new file mode 100644
index 000000000000..f9935e66fc95
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Clock Generator
+
+maintainers:
+ - Chen Wang <unicorn_wang@xxxxxxxxxxx>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-clkgen
+
+ reg:
+ maxItems: 1
+
+ sophgo,system-ctrl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to SG2042 System Controller node. On SG2042, part of control
+ registers of Clock Controller are defined in System controller. Clock
+ driver will use this phandle to get the register map base to plus the
+ offset of the registers to access them.
Do not describe the driver, but hardware. What registers are in
system-ctrl? What are their purpose? Why this hardware needs them?
Understood, will fix the words in revision, thanks.
Best regards,
Krzysztof
