On Tue, Jan 20, 2015 at 10:05 AM, Viet Nga Dao <vndao@xxxxxxxxxx> wrote: > On Thu, Jan 15, 2015 at 5:27 PM, Viet Nga Dao <vndao@xxxxxxxxxx> wrote: >> On Tue, Jan 13, 2015 at 11:33 AM, Brian Norris >> <computersforpeace@xxxxxxxxx> wrote: >>> On Thu, Dec 18, 2014 at 12:23:16AM -0800, vndao@xxxxxxxxxx wrote: >>>> From: Viet Nga Dao <vndao@xxxxxxxxxx> >>>> >>>> Altera EPCQ Controller is a soft IP which enables access to Altera EPCQ and >>>> EPCS flash chips. This patch adds driver for these devices. >>>> >>>> Signed-off-by: Viet Nga Dao <vndao@xxxxxxxxxx> >>> >>> This drivers seems awfully similar to (and so I infer it is likely >>> copy-and-pasted from) m25p80.c / spi-nor.c. Do you think it can be >>> rewritten as a SPI NOR driver, under drivers/mtd/spi-nor/ ? It looks >>> like these flash share most (all?) the same basic opcodes. >>> >> For Altera EPCQ flashes, almost operations are performed underline >> hardware. Software only able to perform the following through >> registers: >> - read status register >> - read id >> - write status registers bit SR_BP0,SR_BP1, SR_BP2,SR_BP3, SR_TB >> (http://www.altera.com.my/literature/hb/cfg/cfg_cf52012.pdf) >> For read/write data: all the operations like QUAD_READ/WRITE, >> FAST_READ/WRITE are handled by hardware as well. From software point >> of view, there is no difference between these 2 modes. >> That is why if rewrite the drivers to follow spi-nor structure, it >> will require extra decoding works for the only few used opcodes. >> > Is it OK to remain this driver structure? Can someone please reply my question as it is been a while? Viet Nga -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
