Hi,
Yes, we don't really care about this corner case.
Thanks for your reviewing.
BR
Gabriel
On 17 December 2014 at 15:01, One Thousand Gnomes
<gnomes@xxxxxxxxxxxxxxxxxxx> wrote:
> On Wed, 17 Dec 2014 11:34:46 +0100
> Gabriel FERNANDEZ <gabriel.fernandez@xxxxxx> wrote:
>
>> sti SoCs PCIe IPs are built around DesignWare IP Core.
>> But in these SoCs, PCIe IP doesn't support IO.
>> By default, when no IO space is provided, a default one is assigned.
>>
>> Add an empty IO resource to the bus, and disable IO by default.
>
> As a point of PCI pedantry I don't think this is quite sufficient. PCI
> has a weird corner case where I/O resources are implied rather than
> allocated.
>
> For IDE/SATA you may need to something like
>
> if (class == PCI_CLASS_STORAGE_IDE) {
> u8 progif;
> pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
> progif |= 5;
> pci_write_config_byte(dev, PCI_CLASS_PROG, &progif);
> }
>
> so that any adapter is kicked out of legacy mode and doesn't get implied
> I/O resources and interrupts. I don't know if that case matters for your
> usage.
>
>
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