> -----Original Message----- > From: Samuel Holland <samuel.holland@xxxxxxxxxx> > Sent: Wednesday, December 27, 2023 2:07 AM > To: JeeHeng Sia <jeeheng.sia@xxxxxxxxxxxxxxxx> > Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; Leyfoon Tan > <leyfoon.tan@xxxxxxxxxxxxxxxx>; kernel@xxxxxxxx; conor@xxxxxxxxxx; robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx; > paul.walmsley@xxxxxxxxxx; palmer@xxxxxxxxxxx; aou@xxxxxxxxxxxxxxxxx; mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxx; > p.zabel@xxxxxxxxxxxxxx; emil.renner.berthing@xxxxxxxxxxxxx; Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>; Xingyu Wu > <xingyu.wu@xxxxxxxxxxxxxxxx> > Subject: Re: [RFC 07/16] dt-bindings: clock: Add StarFive JH8100 North-West clock and reset generator > > On 2023-12-25 11:38 PM, Sia Jee Heng wrote: > > Add bindings for the North-West clock and reset generator (NWCRG) on > > JH8100 SoC. > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@xxxxxxxxxxxxxxxx> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx> > > --- > > .../bindings/clock/starfive,jh8100-nwcrg.yaml | 119 ++++++++++++++++++ > > .../dt-bindings/clock/starfive,jh8100-crg.h | 43 +++++++ > > .../dt-bindings/reset/starfive,jh8100-crg.h | 14 +++ > > 3 files changed, 176 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml > > > > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml > b/Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml > > new file mode 100644 > > index 000000000000..be0f94e64e6a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml > > @@ -0,0 +1,119 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/starfive,jh8100-nwcrg.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: StarFive JH8100 North-West Clock and Reset Generator > > + > > +maintainers: > > + - Sia Jee Heng <jeeheng.sia@xxxxxxxxxxxxxxxx> > > + > > +properties: > > + compatible: > > + const: starfive,jh8100-nwcrg > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Main Oscillator (24 MHz) > > + - description: APB_BUS clock from SYSCRG > > + - description: APB_BUS_PER4 clock from SYSCRG > > + - description: SPI_CORE_100 clock from SYSCRG > > + - description: ISP_2X clock from SYSCRG > > + - description: ISP_AXI clock from SYSCRG > > + - description: VOUT_ROOT0 clock from SYSCRG > > + - description: VOUT_ROOT1 clock from SYSCRG > > + - description: VOUT_SCAN_ATS clock from SYSCRG > > + - description: VOUT_DC_CORE clock from SYSCRG > > + - description: VOUT_AXI clock from SYSCRG > > + - description: AXI_400 clock from SYSCRG > > + - description: AHB0 clock from SYSCRG > > + - description: PERH_ROOT_PREOSC from SYSCRG > > + - description: External DVP clock > > + - description: External ISP DPHY TAP TCK clock > > + - description: External golbal clock > > Typo: global Oops. Will fix it. Thanks. > > > + - description: External VOUT MIPI DPHY TAP TCK > > + - description: External VOUT eDP TAP TCK > > + - description: External SPI In2 clock > > + - description: PLL5 > > [...]
