snps,dw-pcie.yaml already have reg and reg-name information. Needn't
duplciate here.
Acked-by: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
---
Notes:
Change from v4 to v5
- add Rob's Acked
Change from v1 to v4:
- new patch at v4
.../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 81bbb8728f0f9..f20d4f0e3cb6c 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -30,16 +30,6 @@ properties:
- fsl,imx8mm-pcie
- fsl,imx8mp-pcie
- reg:
- items:
- - description: Data Bus Interface (DBI) registers.
- - description: PCIe configuration space region.
-
- reg-names:
- items:
- - const: dbi
- - const: config
-
clocks:
minItems: 3
items:
--
2.34.1
