On Thu, 09 Nov 2023 09:15:09 PST (-0800), Conor Dooley wrote:
On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote:
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor.
Signed-off-by: Michal Simek <michal.simek@xxxxxxx>
Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
I thought I had already done so, but must have forgot to actually send
the email.
Conor asked me to pick it up, it's over staged for testing. Pretty much
no chance it fails anything, so should show up on for-next soon.
Cheers,
Conor.
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 97e8441eda1c..7b077af62b27 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -32,6 +32,7 @@ properties:
oneOf:
- items:
- enum:
+ - amd,mbv32
- andestech,ax45mp
- canaan,k210
- sifive,bullet0
--
2.36.1
