Hi Conor:
On Tue, Dec 19, 2023 at 10:05 PM Conor Dooley <conor@xxxxxxxxxx> wrote:
>
> On Mon, Dec 18, 2023 at 09:52:58AM +0800, Binbin Zhou wrote:
> > diff --git a/arch/loongarch/boot/dts/loongson-2k0500.dtsi b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
> > new file mode 100644
> > index 000000000000..1dcb6a20fc6c
> > --- /dev/null
> > +++ b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
> > @@ -0,0 +1,274 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2023 Loongson Technology Corporation Limited
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu0>;
> > + };
> > + };
> > + };
>
> You have only one CPU, this should not be needed.
OK!
>
> > +
> > + cpu0: cpu@0 {
> > + compatible = "loongson,la264";
> > + device_type = "cpu";
> > + reg = <0x0>;
> > + clocks = <&cpu_clk>;
>
> Is this actually a complete description of the cpu? Are there i/d caches
> etc?
The cpu i/d caches are present, but the architecture gets the values
through a particular instruction (`cpucfg`). So I didn't describe it
here.
Thanks.
Binbin
>
> Cheers,
> Conor.
