Hi Alexander,
>
> Hi,
>
> thanks for the patch.
>
> Am Donnerstag, 14. Dezember 2023, 12:24:41 CET schrieb Xu Yang:
> > There are 2 USB controllers on i.MX93. Add them.
> >
> > Signed-off-by: Xu Yang <xu.yang_2@xxxxxxx>
> > ---
> > arch/arm64/boot/dts/freescale/imx93.dtsi | 58 ++++++++++++++++++++++++
> > 1 file changed, 58 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi
> > b/arch/arm64/boot/dts/freescale/imx93.dtsi index 34c0540276d1..bcf4861cfede
> > 100644
> > --- a/arch/arm64/boot/dts/freescale/imx93.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
> > @@ -171,6 +171,20 @@ cm33: remoteproc-cm33 {
> > status = "disabled";
> > };
> >
> > + usbphynop1: usbphynop1 {
> > + #phy-cells = <0>;
> > + compatible = "usb-nop-xceiv";
>
> compatible first.
Okay.
>
> > + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
> > + clock-names = "main_clk";
> > + };
> > +
> > + usbphynop2: usbphynop2 {
> > + #phy-cells = <0>;
> > + compatible = "usb-nop-xceiv";
>
> compatible first.
Okay.
>
> > + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
> > + clock-names = "main_clk";
> > + };
> > +
> > soc@0 {
> > compatible = "simple-bus";
> > #address-cells = <1>;
> > @@ -1059,5 +1073,49 @@ ddr-pmu@4e300dc0 {
> > reg = <0x4e300dc0 0x200>;
> > interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> > };
> > +
> > + usbotg1: usb@4c100000 {
> > + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb",
> "fsl,imx27-usb";
> > + reg = <0x4c100000 0x200>;
> > + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
> > + <&clk IMX93_CLK_HSIO_32K_GATE>;
> > + clock-names = "usb_ctrl_root_clk",
> "usb_wakeup_clk";
>
> drivers/usb/chipidea/ci_hdrc_imx.c uses 3 clocks: "ipg", "ahb" and "per", see
> imx_get_clks(). How is this supposed to work?
I have sent another patch to get this clock.
https://lore.kernel.org/all/20231214112622.2412321-1-xu.yang_2@xxxxxxx/
>
> > + assigned-clocks = <&clk IMX93_CLK_HSIO>;
> > + assigned-clock-parents = <&clk
> IMX93_CLK_SYS_PLL_PFD1_DIV2>;
> > + assigned-clock-rates = <133000000>;
> > + fsl,usbphy = <&usbphynop1>;
> > + fsl,usbmisc = <&usbmisc1 0>;
> > + status = "disabled";
> > + };
> > +
> > + usbmisc1: usbmisc@4c100200 {
> > + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-
> usbmisc",
> > + "fsl,imx6q-usbmisc";
>
> This means you are compatible to fsl,imx7d-usbmisc. Which means you use
> register MX7D_USB_OTG_PHY_STATUS in USB misc (USBNC). But i.MX93 RM Rev. 2
> (04/2023) lacks this and other registers.
Some registers in USBNC are not shown. The internal RM has these registers.
>
> > + #index-cells = <1>;
> > + reg = <0x4c100200 0x200>;
>
> reg after compatible.
Okay.
>
> > + };
> > +
> > + usbotg2: usb@4c200000 {
> > + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb",
> "fsl,imx27-usb";
> > + reg = <0x4c200000 0x200>;
> > + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
> > + <&clk IMX93_CLK_HSIO_32K_GATE>;
> > + clock-names = "usb_ctrl_root_clk",
> "usb_wakeup_clk";
>
> The same as for usbotg1 applies here.
Okay.
>
> > + assigned-clocks = <&clk IMX93_CLK_HSIO>;
> > + assigned-clock-parents = <&clk
> IMX93_CLK_SYS_PLL_PFD1_DIV2>;
> > + assigned-clock-rates = <133000000>;
> > + fsl,usbphy = <&usbphynop2>;
> > + fsl,usbmisc = <&usbmisc2 0>;
> > + status = "disabled";
> > + };
> > +
> > + usbmisc2: usbmisc@4c200200 {
> > + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-
> usbmisc",
> > + "fsl,imx6q-usbmisc";
> > + #index-cells = <1>;
> > + reg = <0x4c200200 0x200>;
>
> The same as for usbmisc1 applies here.
Okay.
>
> > + };
> > };
> > };
>
> Best regards,
> Alexander
>
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