Hi Conor, On Wed, Dec 13, 2023 at 4:43 PM Conor Dooley <conor@xxxxxxxxxx> wrote: > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote: > > Now that the driver for the SiFive cache controller supports manual > > flushing as non-standard cache operations[1] we can add an errata option > > for the StarFive JH7100 SoC and update the device tree with the cache > > controller, dedicated DMA pool and add MMC nodes for the SD-card and > > wifi. > > > > This series needs the following commit in [1] to work properly: > > > > [...] > > Applied to riscv-cache-for-next, thanks! > > [1/8] riscv: errata: Add StarFive JH7100 errata > https://git.kernel.org/conor/c/64fc984a8a54 That's the one which also needs depends on !DMA_DIRECT_REMAP? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
