On Thu, Dec 7, 2023 at 8:08 AM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> Some of the Ethernet pins on RZ/G3S (but also valid for RZ/G2L) need to
> have the direction of the IO buffer set as output for Ethernet to work
> properly. On RZ/G3S, these pins are P1_0/P7_0, P1_1/P7_1 which could have
> the following Ethernet functions: TXC/TX_CLK or TX_CTL/TX_EN.
>
> As the pins supporting output enable are SoC specific and there is a
> limited number of these pins (TXC/TX_CLK and/or TX_CTL/TX_EN), for proper
> validation the output enable capable port limits were specified on
> platform-based configuration data structure.
>
> The OEN support has been intantiated for RZ/G3S at the moment.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> ---
>
> Changes in v2:
> - use 8 bit helpers to get/set value of output enable register
> - adapted to code to work for both RZ/G2L based devices and RZ/G3S
> - removed IEN capability for Ethernet pins and added it in a separate
> patch (patch 07/12)
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-pinctrl-for-v6.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
