> -----Original Message----- > From: Conor Dooley <conor@xxxxxxxxxx> > Sent: Wednesday, December 13, 2023 8:43 PM > To: JeeHeng Sia <jeeheng.sia@xxxxxxxxxxxxxxxx> > Cc: kernel@xxxxxxxx; robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx; > krzk@xxxxxxxxxx; conor+dt@xxxxxxxxxx; paul.walmsley@xxxxxxxxxx; > palmer@xxxxxxxxxxx; aou@xxxxxxxxxxxxxxxxx; daniel.lezcano@xxxxxxxxxx; > tglx@xxxxxxxxxxxxx; anup@xxxxxxxxxxxxxx; gregkh@xxxxxxxxxxxxxxxxxxx; > jirislaby@xxxxxxxxxx; michal.simek@xxxxxxx; Michael Zhu > <michael.zhu@xxxxxxxxxxxxxxxx>; drew@xxxxxxxxxxxxxxx; > devicetree@xxxxxxxxxxxxxxx; linux-riscv@xxxxxxxxxxxxxxxxxxx; linux- > kernel@xxxxxxxxxxxxxxx; Leyfoon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx>; Conor > Dooley <conor.dooley@xxxxxxxxxxxxx> > Subject: Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC > > On Fri, Dec 01, 2023 at 08:14:06PM +0800, Sia Jee Heng wrote: > > Add device tree bindings for the StarFive JH8100 RISC-V SoC. > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@xxxxxxxxxxxxxxxx> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx> > > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > --- > > Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml > > b/Documentation/devicetree/bindings/riscv/starfive.yaml > > index cc4d92f0a1bf..12d7844232b8 100644 > > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml > > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml > > @@ -30,6 +30,10 @@ properties: > > - starfive,visionfive-2-v1.3b > > - const: starfive,jh7110 > > > > + - items: > > + - enum: > > + - starfive,jh8100-evb > > Hmm, reading some of the other threads it appears that the evaluation > platform that you guys have is actually just an FPGA? Could you please provide > more information as to what this "evb" actually is? > > If it is just an FPGA-based evaluation platform I don't think that we want to > merge patches for the platform. I'm fine with patches adding peripheral > support, but the soc/board dts files and things like pinctrl or clock drivers I am > not keen on. > Perhaps Emil also has an opinion on this. > > Thanks, > Conor. We have been testing on the FPGA/emulator for pre-silicon validation. It will have real silicon SoC next year. Regards Ley Foon
