Hi André, Thanks for the review On Mon, 4 Dec 2023 at 17:51, André Draszik <andre.draszik@xxxxxxxxxx> wrote: > > On Fri, 2023-12-01 at 16:09 +0000, Peter Griffin wrote: > > cmu_top is the top level clock management unit which contains PLLs, muxes, > > dividers and gates that feed the other clock management units. > > > > cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the > > APM module. > > > > Acked-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx> > > Tested-by: Will McVicker <willmcvicker@xxxxxxxxxx> > > Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx> > > --- > > drivers/clk/samsung/Makefile | 1 + > > drivers/clk/samsung/clk-gs101.c | 2495 +++++++++++++++++++++++++++++++ > > 2 files changed, 2496 insertions(+) > > create mode 100644 drivers/clk/samsung/clk-gs101.c > > > > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile > > index ebbeacabe88f..3056944a5a54 100644 > > --- a/drivers/clk/samsung/Makefile > > +++ b/drivers/clk/samsung/Makefile > > @@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o > > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o > > obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > > obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o > > obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o > > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c > > new file mode 100644 > > index 000000000000..6bd233a7ab63 > > --- /dev/null > > +++ b/drivers/clk/samsung/clk-gs101.c > > @@ -0,0 +1,2495 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * Copyright (C) 2023 Linaro Ltd. > > + * Author: Peter Griffin <peter.griffin@xxxxxxxxxx> > > + * > > + * Common Clock Framework support for GS101. > > + */ > > [...] > > + > > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI0 */ > > +PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_shared2_div2" }; > > + > > +PNAME(mout_cmu_hsi0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4", > > + "dout_shared2_div2", "dout_shared3_div2", > > + "fout_spare_pll" }; > > This should also be updated.... > > > [...] > > + MUX(CLK_MOUT_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p, > > + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3), > > ...because we have 8 possibilities now. Interesting, unfortunately there is some discrepancy between the documentation again :( All the cmu_top clock parents were authored using the cmu_diagrams which only shows the 5 parents listed above. Checking the mux register definition it lists 5-7 as being oscclk 5=osclk 6=osclk 7=oscclk Downstream clock implementation lists these oscclk 5-7 as well, so I guess we should add them...sigh > (I didn't check the other parents, but you mentioned you updated field widths > in other registers, too, so maybe need to double check the parent strings as well) Yes I will go through and re-check these parent names again. Peter