Hi Krzysztof, >>> On 01/12/2023 11:52, Tzuyi Chang wrote: >>>> + "#phy-cells": >>>> + const: 0 >>>> + >>>> + nvmem-cells: >>>> + maxItems: 1 >>>> + description: >>>> + Phandle to nvmem cell that contains 'Tx swing trim' >>>> + tuning parameter value for PCIe phy. >>>> + >>>> + nvmem-cell-names: >>>> + items: >>>> + - const: tx_swing_trim >>>> + >>>> + realtek,pcie-syscon: >>>> + $ref: /schemas/types.yaml#/definitions/phandle >>>> + description: phandle of syscon used to control PCIe MDIO register. >>> >>> Why this does not have reg property but syscon? This looks hacky. >>> >> >> Our PCIe PHY driver needs to access two registers: >> 1. PCIe MDIO register: Utilized for configuring the PCIe PHY. >> 2. PCIe MAC Link Control and Link Status Register: Use to get the current >> link speed for calibration purposes. >> >> Both these registers reside within the PCIe controller registers. The >> PCIe driver has mapped these register address region, so I use regmap >> to access these registers. > >Hm, isn't in such case PCIe PHY a child of the PCIe controller? How is it with >resources, like power domains or regulators? In fact, I positioned the PCIe PHY node outside the PCIe controller node. It would be more appropriate for the PCIe PHY as the child node of the PCIe controller. I will revise to this structure. I will also remove the "realtek,pcie-syscon" property and use dev->parent->of_node to get the syscon of the PCIe controller. Since the MDIO register is located within the PCIe controller registers, it can only be accessed after enabling the clock and asserting the resets of the PCIe controller. Therefore, the PCIe PHY driver only registers the callback functions of phy_ops (.init and .calibrate). After the PCIe controller driver sets the clock and resets, it will execute PHY framework API to configure the PHY. Thanks, Tzuyi Chang
