Hello Daniel,
On Wed, 6 Dec 2023 01:44:38 +0000
Daniel Golle <daniel@xxxxxxxxxxxxxx> wrote:
> Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting
> USXGMII, 10GBase-R and 5GBase-R interface modes. In order to support
> Cisco SGMII, 1000Base-X and 2500Base-X via the also present LynxI PCS
> create a wrapped PCS taking care of the components shared between the
> new USXGMII PCS and the legacy LynxI PCS.
>
> Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx>
> ---
[...]
> +
> +static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
> + phy_interface_t interface,
> + const unsigned long *advertising,
> + bool permit_pause_to_mac)
> +{
> + struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
> + unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
> + bool mode_changed = false;
Reverse christmas tree ordering can be used here (longest lines first)
> +
> + if (interface == PHY_INTERFACE_MODE_USXGMII) {
> + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
> + link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
> + FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
> + FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
> + xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
> + FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
> + } else if (interface == PHY_INTERFACE_MODE_10GBASER) {
> + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
> + link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
> + FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
> + FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
> + xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
> + FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
> + adapt_mode = USXGMII_RATE_UPDATE_MODE;
> + } else if (interface == PHY_INTERFACE_MODE_5GBASER) {
> + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
> + link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
> + FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
> + FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
> + xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_5G) |
> + FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_5G);
> + adapt_mode = USXGMII_RATE_UPDATE_MODE;
> + } else {
> + return -EINVAL;
> + }
> +
> + adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
> +
> + if (mpcs->interface != interface) {
> + mpcs->interface = interface;
> + mode_changed = true;
> + }
> +
> + mtk_usxgmii_reset(mpcs);
> +
> + /* Setup USXGMII AN ctrl */
> + mtk_m32(mpcs, RG_PCS_AN_CTRL0,
> + USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
> + an_ctrl);
> +
> + mtk_m32(mpcs, RG_PCS_AN_CTRL2,
> + USXGMII_LINK_TIMER_IDLE_DETECT |
> + USXGMII_LINK_TIMER_COMP_ACK_DETECT |
> + USXGMII_LINK_TIMER_AN_RESTART,
> + link_timer);
> +
> + mpcs->neg_mode = neg_mode;
> +
> + /* Gated MAC CK */
> + mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
> + USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
> +
> + /* Enable interface force mode */
> + mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
> + USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
> +
> + /* Setup USXGMII adapt mode */
> + mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
> + USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
> + adapt_mode);
> +
> + /* Setup USXGMII speed */
> + mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
> + USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
> + xfi_mode);
> +
> + usleep_range(1, 10);
> +
> + /* Un-gated MAC CK */
> + mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_MAC_CK_GATED, 0);
> +
> + usleep_range(1, 10);
> +
> + /* Disable interface force mode for the AN mode */
> + if (an_ctrl & USXGMII_AN_ENABLE)
> + mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_IF_FORCE_EN, 0);
> +
> + return mode_changed;
> +}
> +
[...]
> +static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
> + struct phylink_link_state *state)
> +{
> + struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
> +
> + /* Refresh USXGMII link status by toggling RG_PCS_AN_STATUS_UPDATE */
> + mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE,
> + RG_PCS_RX_STATUS_UPDATE);
> + ndelay(1020);
> + mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE, 0);
> + ndelay(1020);
> +
> + /* Read USXGMII link status */
> + state->link = FIELD_GET(RG_PCS_RX_LINK_STATUS,
> + mtk_r32(mpcs, RG_PCS_RX_STATUS0));
> +
> + /* Continuously repeat re-configuration sequence until link comes up */
> + if (!state->link) {
> + mtk_usxgmii_pcs_config(pcs, mpcs->neg_mode,
> + state->interface, NULL, false);
> + return;
.pcs_get_state() isn't called only for link state polling,but also when querying
the link state from ethtool, from phylink_ethtool_ksettings_get().
As mtk_usxgmii_pcs_config triggers a pcs reset and reconfiguration, won't this disrupt
the link ?
Thanks,
Maxime
