On 11/17/2023 1:20 AM, Andrew Lunn wrote:
FYI, here is the sequence to bring up qca8084.
a. enable clock output to qca8084.
b. do gpio reset of qca8084.
c. customize MDIO address and initialization configurations.
d. the PHY ID can be acquired.
This all sounds like it is specific to the qca8084, so it should be in
the driver for the qca8084.
Its been pointed out you can get the driver to load by using the PHY
ID in the compatible. You want the SoC clock driver to export a CCF
clock, which the PHY driver can use. The PHY driver should also be
able to get the GPIO. So i think the PHY driver can do all this.
Andrew
Hi Andrew,
If i put the GPIO reset in the PHY device tree node, the PHY probe
function will be postponed to be called instead of being called
during the MDIO bus register, which leads to the PCS can't be
created correctly because of reading PHY capability failed before
the PHY probe function called.
my device tree nodes are as below.
ethernet_device {
phy-handle = <&phy3>;
phy-mode = "2500base-x";
...
};
mdio@90000 {
phy3: ethernet-phy@3 {
compatible = "ethernet-phy-id004d.d180";
reg = <4>;
reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
reset-deassert-us = <100000>;
clocks = <...>;
clock-names = "...";
};
};
Since the PHY probe function of phy3 is postponed instead of
called during the MDIO bus driver register, and the initialization
of qca8084 is not called when the ethernet_device driver is called
to create PCS, where the phy3 capability is checked, which is failed
since the qca8084 PHY probe is not called.
Any idea to resolve this call sequence issue?
Thanks.
