For IPQ5332 platform, there are two MAC PCSs, and qca8084 is connected with one of them, qca8084 supports to customize the MDIO address by configuring security register, which also includes GCC module configurable. 1. To provide the clock to the ethernet, the CMN clock needs to be initialized for selecting reference clock and enable the output clock. 2. GCC uniphy AHB/SYS clocks need to be configured and the ethernet LDO needs be enabled to make the GPIO reset of phy taking effect. 3. The MDIO address of qca8084 PHY can be programed with any customized value by configuring the security register which is accessed by the special MDIO sequence. 4. Before the qca8084 PHY probeable by MDIO bus, the related clocks and reset sequence should be completed. 5. Add the example MDIO device tree node for IPQ5018. Luo Jie (9): net: mdio: ipq4019: increase eth_ldo_rdy for ipq5332 platform net: mdio: ipq4019: Enable the clocks for ipq5332 platform net: mdio: ipq4019: Enable GPIO reset for ipq5332 platform net: mdio: ipq4019: configure CMN PLL clock for ipq5332 net: mdio: ipq4019: support MDIO clock frequency divider net: mdio: ipq4019: Support qca8084 switch register access net: mdio: ipq4019: program phy address when "fixup" defined net: mdio: ipq4019: add qca8084 configurations dt-bindings: net: ipq4019-mdio: Document ipq5332 platform .../bindings/net/qcom,ipq4019-mdio.yaml | 138 ++++- drivers/net/mdio/mdio-ipq4019.c | 557 +++++++++++++++++- 2 files changed, 656 insertions(+), 39 deletions(-) base-commit: bc962b35b139dd52319e6fc0f4bab00593bf38c9 -- 2.42.0
