On Fri, Nov 10, 2023 at 03:31:15PM +0530, Krishna Kurapati PSSNV wrote: > Controller-1: > u_usb31_prim_mvs_wrapper_usb31_hs_phy_irq SYS_apcsQgicSPI[806] > Controller-2: > u_usb31_prim_mvs_wrapper_usb31_hs_phy_irq SYS_apcsQgicSPI[791] Thanks. > > Yes, but, again, you never enabled them in the PHY (cf. QUSB2) so it's > > hardly surprising that they do not fire. > > > There is no register in femto phy address space of sc8280 (which I am > currently testing) where we can configure these registers like qusb2 phy's. Right, so they are not enabled (and possibly cannot be enabled). > > So then including the hs_phy_irq for most of these SoCs was a mistake > > and we should drop it from the bindings? > > > > What about the QUSB2 SoCs that also define DP/DM, are both useable > > there? > > > > And if so, is there any reason to prefer one mechanism over the other? > > No. I didn't ask this question to hw team whether dp/dm are used in qusb2 > phy targets. Let me ask them. > > While I do so, since there are no qusb2 targets present on femto phy's, do > you suggest we still add them to port structure in dwc3-qcom ? I am inclined > to add it because it would make implementation look cleaner w.r.t code and > also spurious interrupts are not getting triggered (which was my primary > concern as it was never tested). Yes, that's what I've been suggesting all along. It's a per-port interrupt so that's where it belongs. We should still try to determine when each interrupt should be enabled and how best to implement that (hence all my questions). For example, if there is no use for hs interrupts on SoCs using femto PHYs we should fix the bindings. If we can use dp/dm on SoCs using QUSB2 PHYs, we should probably just ignore the hs interrupt when all three are defined (especially since that functionality has never worked anyway). Johan
