On 11/8/23 09:12, Rob Herring wrote: > On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote: >> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. >> It is hardware compatible with classic MicroBlaze processor. > > How is that possible? It's a different instruction set, right? I suppose > the IP interfaces (signals) are the same/compatible. Coincidentally, I asked myself the same question, so I asked my former manager who designed the ancestor of this processor. The answer is | It is still the same MicroBlaze pipeline just with a different | instruction decoder up front. The “macro ops” are now RISC V | instructions, the “micro-ops” are still the same operations in the | various MicroBlaze pipeline stages. So, yes, all the hardware interface is the same. -- Ronan KERYELL, Research Labs / San José, California. AMD Research and Advanced Development.
