On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote: > MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. > It is hardware compatible with classic MicroBlaze processor. How is that possible? It's a different instruction set, right? I suppose the IP interfaces (signals) are the same/compatible. > > Signed-off-by: Michal Simek <michal.simek@xxxxxxx> > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) Anyways, Acked-by: Rob Herring <robh@xxxxxxxxxx> > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 97e8441eda1c..7b077af62b27 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -32,6 +32,7 @@ properties: > oneOf: > - items: > - enum: > + - amd,mbv32 > - andestech,ax45mp > - canaan,k210 > - sifive,bullet0 > -- > 2.36.1 >
